Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device fabrication method that prevents an arcing failure from occurring in an edge bead removal (EBR) region of a wafer.
As the integration degree of a semiconductor device increases, it is desirable to decrease the line width of metal lines. It has been difficult to use conventional methods for forming the metal lines and satisfy the desired line width of the metal lines. To address these concerns, metal lines have been formed through a Damascene process. According to the Damascene process, a Chemical Mechanical Polishing (CMP) process is performed as a planarization process in order to form metal lines and electrically insulate the metal lines from each other.
FIGS. 1A to 1D are cross-sectional views illustrating a conventional method for forming a metal line.
Referring to FIG. 1A, a first inter-layer dielectric layer is formed over a wafer 11 which has a die region where a semiconductor device is formed and an EBR region on the outskirt of the wafer 11. The first inter-layer dielectric layer is selectively etched to form a plurality of first contact holes 13. Hereafter, the selectively etched first inter-layer dielectric layer will be referred to as a first inter-layer dielectric layer pattern 12.
Subsequently, a conductive layer for plugs is deposited over the wafer 11 to fill the first contact holes 13, and a planarization process, e.g., a CMP process, is performed in such a manner that the upper surface of the first inter-layer dielectric layer pattern 12 is exposed. As a result, plugs 14 are formed.
Referring to FIG. 1B, a second inter-layer dielectric layer is formed over the wafer 11 and the second inter-layer dielectric layer is selectively etched to form trenches 16 for metal lines. Hereafter, the selectively etched second inter-layer dielectric layer will be referred to as a second inter-layer dielectric layer pattern 15.
Subsequently, a metal layer is deposited over the wafer 11 to fill the trenches 16, and a planarization process, e.g., a CMP process, is performed in such a manner that the upper surface of the second inter-layer dielectric layer pattern 15 is exposed. As a result, metal lines 17 are formed.
Referring to FIG. 1C, a third inter-layer dielectric layer 18 is formed over the wafer 11, and a photoresist pattern 19 for forming contact holes which exposes the metal lines 17 is formed over the third inter-layer dielectric layer 18.
Referring to FIG. 1D, the third inter-layer dielectric layer 18 is etched using the photoresist pattern 19 as an etch barrier to form second contact holes 20 which expose the metal lines 17. Herein, the etched third inter-layer dielectric layer 18 will be referred to as a third inter-layer dielectric layer pattern 18A.
When the structures are formed in the die region of the wafer 11 according to the conventional technology, a dummy structure which is the same as the structure formed in the die region is also formed in the EBR region on the outskirt of the wafer 11. This is to prevent a step height between the structures on the wafer 11 and to secure polishing uniformity during the planarization process.
However, since in the EBR region for a dummy structure, a process according to a conventional technology may be performed abnormally, defects such as abnormal formation of the plugs 14 occur frequently due to impurities or other reasons during the formation of the first contact holes 13 and the plugs 14 (see reference symbol ‘A’ of FIG. 1A).
Due to the defect in the formation of the plugs 14, which is connected to the metal lines 17, in the EBR region, a cut-off in the current flow from the metal lines 17 to the wafer 11 in the EBR region may occur, and as a result, there is a concern that an arcing failure occurs due to a potential difference induced during a dry etch process using a plasma etch device (see FIG. 1D).
The arcing refers to a phenomenon that an inter-layer dielectric layer is broken down by high electric power used during the plasma etch process of the inter-layer dielectric. In a severe case, the conductive layer in the lower portion of the inter-layer dielectric layer may be fused or peeling may occur (see reference symbol ‘B ’ of FIG. 1D). Also, the inter-layer dielectric layer broken down due to the arcing phenomenon and the conductive layer in the lower portion of the inter-layer dielectric layer function as particles, and the reliability of the semiconductor device is deteriorated.